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june 2010 doc id 14956 rev 4 1/51 51 AIS326DQ mems inertial sensor 3-axis, low g accelerometer with digital output features 3.3 v single supply operation 1.8 v compatible ios spi digital output interface 12 bit resolution interrupt activated by motion programmable interrupt threshold embedded self-test high shock survivability ecopack ? compliant extended temperature range -40 c to +105 c applications anti-theft systems and inertial navigation motion activated functions vibration monitoring and compensation tilt measurements black boxes, ev ent recorders description the AIS326DQ is a three axes digital output accelerometer that includes a sensing element and an ic interface able to take the information from the sensing element and to provide the measured acceleration signals to the external world through an spi serial interface. i 2 c compatible interface is also available. the sensing element, capable of detecting the acceleration, is manufactured using a dedicated process developed by st to produce inertial sensors and actuators in silicon. the ic interface instead is manufactured using a cmos process that allows high level of integration to design a dedicated circuit which is factory trimmed to better match the sensing element characteristics. the AIS326DQ has a user selectable full scale of 2 g , 6 g and it is capable of measuring acceleration over a bandwidth of 640 hz for all axes. the device bandwidth may be selected accordingly to the application requirements. the self-test capability allows the user to check the functioning of the system. the device is available in plastic quad flat package no lead surface mount (qfpn) and it is specified over a temperature range extending from -40 c to +105 c. qfpn-28 table 1. device summary order code operating temperature range [ c] package packing AIS326DQ -40 to +105 qfpn-28 tray AIS326DQtr -40 to +105 qfpn-28 tape and reel www.st.com
contents AIS326DQ 2/51 doc id 14956 rev 4 contents 1 block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.2 qfpn-28 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 mechanical and electrical specifications . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 mechanical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 communication interface characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3.1 spi - serial peripheral interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.1 sensitivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.2 zero-g level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.3 self test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 sensing element . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 ic interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 factory calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5 digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1 spi bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.1.1 spi read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.1.2 spi write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1.3 spi read in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 register mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.1 who_am_i (0fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.2 offset_x (16h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
AIS326DQ contents doc id 14956 rev 4 3/51 7.3 offset_y (17h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7.4 offset_z (18h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.5 gain_x (19h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.6 gain_y (1ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.7 gain_z (1bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.8 ctrl_reg1 (20h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.9 ctrl_reg2 (21h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.10 ctrl_reg3 (22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 7.11 hp_filter_reset (23h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.12 status_reg (27h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.13 outx_l (28h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.14 outx_h (29h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.15 outy_l (2ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.16 outy_h (2bh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.17 outz_l (2ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.18 outz_h (2dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.19 ff_wu_cfg (30h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 7.20 ff_wu_src (31h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.21 ff_wu_ack (32h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.22 ff_wu_ths_l (34h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.23 ff_wu_ths_h (35h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 7.24 ff_wu_duration (36h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.25 dd_cfg (38h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 7.26 dd_src (39h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 7.27 dd_ack (3ah) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.28 dd_thsi_l (3ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.29 dd_thsi_h (3dh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.30 dd_thse_l (3eh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 7.31 dd_thse_h (3fh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8 typical performance characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.1 mechanical characteristics at 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.2 mechanical characteristics at -40 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
contents AIS326DQ 4/51 doc id 14956 rev 4 8.3 mechanical characteristics at 105 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 8.4 mechanical characteristics derived from measurement in the -40 c to +105 c temperature range 43 8.5 electro-mechanical characteristics at 25 c . . . . . . . . . . . . . . . . . . . . . . . 44 8.6 electrical characteristics at 25 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.7 electrical characteristics at -40 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8.8 electrical characteristics at 105 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9 soldering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 general guidelines about soldering surface mount accelerometer . . . . . 46 9.2 pcb design guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2.1 pcb design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 9.3 stencil design and solder paste application . . . . . . . . . . . . . . . . . . . . . . . 47 9.4 process consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 11 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
AIS326DQ list of tables doc id 14956 rev 4 5/51 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 table 3. mechanical characteristics @ vdd = 3.3 v, t = -40 c to 105 c unless otherwise noted. . 7 table 4. electrical characteristics @ vdd=3.3 v, t = -40 c to 105 c unless otherwise noted . . . . 9 table 5. spi slave timing values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. serial interface pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 8. registers address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 10. register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 11. offset_x register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 12. offset_x register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 13. offset_y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 14. offset_y register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 15. offset_z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 16. offset_z register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 17. gain_x register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 18. gain_x register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 19. gain_y register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 20. gain_y register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 21. gain_z register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 22. gain_z register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 23. ctrl_reg1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 24. ctrl_reg1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 25. ctrl_reg2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 26. ctrl_reg2 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 table 27. ctrl_reg3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 28. ctrl_reg3 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 29. status_reg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 30. status_reg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 31. outx_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 32. outx_l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 33. outx_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 34. outx_h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 35. outy_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 36. outy_l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 37. outy_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 38. outy_h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 39. outz_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 40. outz_l register description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 41. outz_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 42. outz_h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 43. ff_wu_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 44. ff_wu_cfg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 table 45. ff_wu_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 46. ff_wu_src register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 table 47. ff_wu_ths_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 48. ff_wu_ths_l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
list of tables AIS326DQ 6/51 doc id 14956 rev 4 table 49. ff_wu_ths_h register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 50. ff_wu_ths_h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 51. ff_wu_duration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 52. ff_wu_duration register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 53. dd_cfg register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 54. dd_cfg register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 table 55. dd_src register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 56. dd_src register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 57. dd_thsi_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 58. dd_thsi_l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 59. dd_thsi_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 60. dd_thsi_h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 61. dd_thse_l register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 62. dd_thse_l register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 63. dd_thse_h register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 64. dd_thse_h register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 65. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
AIS326DQ list of figures doc id 14956 rev 4 7/51 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. spi slave timing diagram (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. AIS326DQ electrical connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. read and write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 6. spi read protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 7. multiple bytes spi read protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 8. spi write protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. multiple bytes spi write protocol (2 bytes example) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 10. spi read protocol in 3-wires mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11. x-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 12. x-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 13. y-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 14. y-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 15. z-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 16. z-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 17. x-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 18. x-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 19. y-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 20. y-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 21. z-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 22. z-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 23. x-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 24. x-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 25. y-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 26. y-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 27. z-axis zero-g level at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 28. z-axis sensitivity at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 29. x-axis zero-g level change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 30. x-axis sensitivity change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 31. y-axis zero-g level change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 32. y-axis sensitivity change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 33. z-axis zero-g level change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 34. z-axis sensitivity change vs. temperature at 3.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 35. x and y axes zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 36. x and y axes sensitivity as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 37. z axis zero-g level as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 38. z axis sensitivity as function of supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 0 figure 39. current consumption in power-down mode (vdd=3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 40. current consumption in operational mode (vdd=3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 41. current consumption in power-down mode (vdd=3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 42. current consumption in operational mode (vdd=3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 43. current consumption in power-down mode (vdd=3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 44. current consumption in operational mode (vdd=3.3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 45. recommended land and solder mask design for qfpn packages . . . . . . . . . . . . . . . . . . 43 figure 46. qfpn-28 mechanical data and package dimensions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
block diagram and pin description AIS326DQ 8/51 doc id 14956 rev 4 1 block diagram and pin description 1.1 block diagram figure 1. block diagram 1.2 qfpn-28 pin description figure 2. pin connection ? charge amplifier mux y+ z+ y- z- regs a x+ x- de mux reconstruction filter ? ? array spi cs spc sdo/sdi sdo control logic & interrupt gen. rdy/int reconstruction filter reconstruction filter clock trimming circuits reference self test AIS326DQ nc gnd reserved vdd gnd rdy/int nc nc reserved reserved vdd gnd ck nc nc sdo vdd_io sdi/sdo spc cs nc nc nc nc nc nc nc nc 1 7 28 22 21 15 814 y 1 x z directions of the detectable accelerations (top view)
AIS326DQ block diagram and pin description doc id 14956 rev 4 9/51 table 2. pin description pin# name function 1 nc internally not connected 2 gnd 0 v supply 3 vdd power supply 4 reserved either leave unconnected or connect to gnd 5 gnd 0 v supply 6 rdy/int data ready/inertial wake-up and free-fall interrupt 7, 8 nc internally not connected 9 sdo spi serial data output 10 sdi/ sdo spi serial data input (sdi) 3-wire interface serial data output (sdo) 11 vdd_io power supply for i/o pads 12 spc spi serial port clock 13 cs chip select (logic 0: spi enabled, logic 1: spi disabled) 14, 15 nc internally not connected 16 ck optional external clock, if not used either leave unconnected or connect to gnd 17 gnd 0 v supply 18 reserved either leave uncon nected or connect to vdd_io 19 vdd power supply 20 reserved connect to vdd 21 - 28 nc internally not connected
mechanical and electrical specifications AIS326DQ 10/51 doc id 14956 rev 4 2 mechanical and electrical specifications 2.1 mechanical characteristics table 3. mechanical characteristics @ vdd = 3.3 v, t = -40 c to 105 c unless otherwise noted (1) symbol parameter test conditions min. typ. (2) max. unit fs measurement range (3) fs bit set to 0 1.7 2.0 g fs bit set to 1 5.3 6.0 dres device resolution full-scale = 2 g t = 25 c, odr1=40 hz 1.0 mg full-scale = 2 g t = 25 c, odr2=160 hz 2.0 full-scale = 2 g t = 25 c, odr3 = 640 hz 3.9 full-scale = 2 g t = 25 c, odr4 = 2560 hz 15.6 so sensitivity full-scale = 2 g 12 bit representation 952 1024 1096 lsb/g full-scale = 6 g 12 bit representation (4) 316 340 364 tcso sensitivity change vs temperature full-scale = 2 g 12 bit representation 0.025 %/ c off zero-g level offset accuracy (5),(6) full-scale = 2 g x, y axis -100 100 mg full-scale = 2 g z axis -200 200 full-scale = 6 g x, y axis (4) -100 100 full-scale = 6 g z axis (4) -200 200 tcoff zero-g level change vs temperature max delta from 25 c 0.2 mg/ c nl non linearity (4) best fit straight line x, y axis full-scale = 2 g odr = 40 hz 2 % fs best fit straight line z axis full-scale = 2 g odr = 40 hz 3 crax cross axis (4) -5 5 %
AIS326DQ mechanical and electrical specifications doc id 14956 rev 4 11/51 v st self-test output change (7),(8) full-scale= 2 g x axis 200 460 750 lsb full-scale= 2 g y axis 200 460 750 full-scale= 2 g z axis 140 360 580 full-scale= 6 g x axis 60 160 260 lsb full-scale= 6 g y axis 60 160 260 full-scale= 6 g z axis 45 120 200 bw system bandwidth (9) odrx/4 hz t op operating temperature range -40 +105 c wh product weight 0.2 gram 1. the product is factory calibrated at 3.3 v. operation over 3.6 v is not recommended 2. typical specificat ions are not guaranteed 3. verified by wafer level test and specif ication of initial offset and sensitivity 4. guaranteed by design 5. zero-g level offset value after msl3 preconditioning 6. offset can be eliminated by enabling the built-in high pass filter (hpf) 7. self test output changes with the power supply. ?self-test output change? is defined as output[lsb] (self-test bit on ctrl_reg1=1) - output[lsb] (self-test bit on ctrl_reg1=0) . 1lsb = 1g/1024 at 12 bit representation, 2 g full-scale 8. output data reach 99% of final value after 5/odr when enabling self-test mode due to device filtering 9. odrx is output data rate. refer to table 4 for specifications table 3. mechanical characteristics @ vdd = 3.3 v, t = -40 c to 105 c unless otherwise noted (1) (continued) symbol parameter test conditions min. typ. (2) max. unit
mechanical and electrical specifications AIS326DQ 12/51 doc id 14956 rev 4 2.2 electrical characteristics table 4. electrical characteristics @ vdd=3.3 v, t = -40 c to 105 c unless otherwise noted (1) symbol parameter test conditions min. typ. (2) max. unit vdd supply voltage 3.0 3.3 3.6 v vdd_io i/o pads supply voltage (3) 1.71 vdd v idd supply current vdd = 3.3 v 0.67 0.80 ma iddpdn current consumption in power-down mode 220a vih digital high level input voltage (3) 0.8*vdd_io v vil digital low level input voltage (3) 0.2*vdd_io voh high level output voltage (3) 0.9*vdd_io v vol low level output voltage (3) 0.1*vdd_io odr1 output data rate 1 dec factor = 512 40 hz odr2 output data rate 2 dec factor = 128 160 odr3 output data rate 3 dec factor = 32 640 odr4 output data rate 4 dec factor = 8 2560 bw system bandwidth (4) odrx/4 hz ton turn-on time (5) 5/odrx s t op operating temperature range -40 +105 c 1. the product is factory calibrated at 3.3 v. operation over 3.6 v is not recommended 2. typical specificat ions are not guaranteed 3. guaranteed by design 4. digital filter -3 db frequency 5. time to obtain valid data after exiting power-down mode
AIS326DQ mechanical and electrical specifications doc id 14956 rev 4 13/51 2.3 communication interface characteristics 2.3.1 spi - serial peripheral interface subject to general operating conditions for vdd and t op . figure 3. spi slave timing diagram (2) 2. measurement points are done at 0.2vdd_io and 0.8vdd_io, for both input and output port 3. when no communication is on-going, data on cs, spc, sdi and sdo are driven by internal pull-up resistors table 5. spi slave timing values symbol parameter value (1) 1. values are guaranteed at 8 mhz clock frequency for spi with both 4 and 3 wires, based on characterization results, not tested in production unit min max tc(spc) spi clock cycle 125 ns fc(spc) spi clock frequency 8 mhz tsu(cs) cs setup time 5 ns th(cs) cs hold time 10 tsu(si) sdi input setup time 5 th(si) sdi input hold time 15 tv(so) sdo valid output time 55 th(so) sdo output hold time 7 tdis(so) sdo output disable time 50 spc cs sdi sdo t su(cs) t v(so) t h(so) t h(si) t su(si) t h(cs) t dis(so) t c(spc) msb in msb out lsb out lsb in (3) (3) (3) (3) (3) (3) (3) (3)
mechanical and electrical specifications AIS326DQ 14/51 doc id 14956 rev 4 2.4 absolute maximum ratings stresses above those listed as ?absolute ma ximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device under these conditions is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. table 6. absolute maximum ratings symbol ratings maximum value unit vdd supply voltage (1) 1. supply voltage on any pin should never exceed 6.0 v. -0.3 to 6.0 v vdd_io i/o pins supply voltage (1) -0.3 to vdd +0.1 v vin input voltage on any control pin (1) (cs, spc, sdi/sdo, sdo, ck) -0.3 to vdd_io +0.3 v a pow acceleration (any axis, powered, vdd = 3.3 v) 3000 g for 0.5 ms 10000 g for 0.1 ms a unp acceleration (any axis, unpowered) 3000 g for 0.5 ms 10000 g for 0.1 ms t op operating temperature range -40 to +105 c t stg storage temperature range -40 to +125 c esd electrostatic discharge protection 4.0 (hbm) kv 200 (mm) v 1.5 (cdm) kv this is a mechanical shock sensitive device, improper handling can cause permanent damages to the part. this is an esd sensitive device, improper handling can cause permanent damages to the part.
AIS326DQ mechanical and electrical specifications doc id 14956 rev 4 15/51 2.5 terminology 2.5.1 sensitivity sensitivity describes the gain of the sensor and can be determined e.g. by applying 1 g acceleration to it. as the sensor can measur e dc accelerations this can be done easily by pointing the axis of interest towards the center of the earth, noting the output value, rotating the sensor by 180 degrees (point to the sky) and noting the output value again. by doing so, 1 g acceleration is applied to the sensor. subtracting the larger output value from the smaller one, and dividing the result by 2, leads to the actual sensitivity of the sensor. this value changes very little over temperature and also very little over time. the sensitivity tolerance describes the range of sensitivities of a large population of sensors. 2.5.2 zero-g level zero- g level offset (off) describes the deviation of an actual output signal from the ideal output signal if there is no acceleration present. a sensor in a steady state on a horizontal surface will measure 0 g in x axis and 0 g in y axis whereas the z axis will measure 1 g . the output is ideally in the middle of the dynamic range of the sensor (content of out registers 00h, 00h with 16 bit representation, data expressed as 2?s complement number). a deviation from ideal value in this case is called zero- g offset. offset is to some extent a result of stress to a precise mems sensor and therefore the of fset can slightly change after mounting the sensor onto a printed circuit board or exposing it to extensive mechanical stress. offset changes little over temperature, see ?zero- g level change vs. temperature?. the zero- g level of an individual sensor is stable over lifetime. the zero- g level tolerance describes the range of zero- g levels of a population of sensors. 2.5.3 self test self test allows to test the mechanical and el ectric part of the sensor, allowing the seismic mass to be moved by means of an electrostatic test-force. the self-test function is off when the self-test bit of ctrl_reg1 (control register 1) is programmed to ?0?. when the self-test bit of ctrl_reg1 is programmed to ?1?an actuation force is applied to the sensor, simulating a definite input acceleration. in this case the sensor outputs will exhibit a change in their dc levels which is related to the selected full scale and depending on the supply voltage through the device sensitivity. when self test is activated, the device output level is given by the algebraic sum of the signals produced by the acceleration acting on the sensor and by the electrostatic test-force. if the output signals change within the amplitude specified inside table 3 or 4 then the sensor is working properly and the parameters of the interface chip are within the defined specification.
functionality AIS326DQ 16/51 doc id 14956 rev 4 3 functionality the AIS326DQ is a high performance, low-power, digital output 3-axes linear accelerometer packaged in a qfn package. the complete device includes a sensing element and an ic interface able to take the information from the sensing element and to provide a signal to the external world through an spi serial interface. 3.1 sensing element a proprietary process is used to create a surface micro-machined accelerometer. the technology allows to carry out suspended s ilicon structures which are attached to the substrate in a few points called anchors and are free to move in the direction of the sensed acceleration. to be compatible with the traditional packaging techniques a cap is placed on top of the sensing element to avoid blocking the moving parts during the moulding phase of the plastic encapsulation. when an acceleration is applied to the sensor the proof mass displaces from its nominal position, causing an imbalance in the capacit ive half-bridge. this imbalance is measured using charge integration in response to a voltage pulse applied to the sense capacitor. at steady state the nominal value of the capacitors are few pf and when an acceleration is applied the maximum variation of the capacitive load is up to 100 pf. 3.2 ic interface the complete measurement chain is composed by a low-noise capacitive amplifier which converts into an analog voltage the capacitive unbalancing of the mems sensor and by three ? analog-to-digital converters, one for each axis, that translate the produced signal into a digital bitstream. the ? converters are coupled with dedicated reconstruction filters which remove the high frequency components of the quantization noise and provide low rate and high resolution digital words. the charge amplifier and the ? converters are operated respectively at 61.5 khz and 20.5 khz. the data rate at the output of the reconstruction depends on the user selected decimation factor (df) and spans from 40 hz to 2560 hz. the acceleration data may be accessed through an spi interface thus making the device particularly suitable for direct interfacing with a microcontroller. the AIS326DQ features a data-ready signal (rdy) which indicates when a new set of measured acceleration data is available thus simplifying data synchronization in digital system employing the device itself. the AIS326DQ may also be configured to generate an inertial wake-up, direction detection and free-fall interrupt signal accordingly to a programmed acceleration event along the enabled axes.
AIS326DQ functionality doc id 14956 rev 4 17/51 3.3 factory calibration the ic interface is factory calibrated for sensitivity (so) and zero- g level (off). the trimming values are stored inside the device by a non volatile structure. any time the device is turned on, the trimming parameters are downloaded into the registers to be employed during the normal operation. this allows the user to employ the device without further calibration.
application hints AIS326DQ 18/51 doc id 14956 rev 4 4 application hints figure 4. AIS326DQ electrical connection the device core is supplied through vdd line while the i/o pads are supplied through vdd_io line. power supply decoupling capacitors (100 nf ceramic, 10 f al) should be placed as near as possible to the pin 3 of the device (common design practice). all the voltage and ground supplies must be present at the same time to have proper behavior of the ic (refer to figure 4 ). it is possible to re move vdd maintaining vdd_io without blocking the communication busses. in this condition the measurement chain is powered off. the functionality of the device and the measured acceleration data is selectable and accessible through the spi interface. the design of the application board should take in consideration that the AIS326DQ is equipped also with an i2c compatible interface that it is activated when the signal on cs pin is high (logic:1). the functions, the thresholds and the timing of the interrupt pin (int) can be completely programmed by the user through the spi interface. AIS326DQ 1 7 28 22 21 15 814 directions of the detectable accelerations vdd_io cs spc sdi/sdo sdo rdy/int 10uf vdd digital signal from/to signal controller. signal?s levels are defined by proper selection of vdd_io 100nf gnd (top view) y 1 x z
AIS326DQ digital interface doc id 14956 rev 4 19/51 5 digital interface the registers embedded inside the AIS326DQ may be accessed through spi serial interface. the latter may be sw configured to operate either in 3-wire or 4-wire interface mode. the embedded registers may be accessed also through an i 2 c interface. for i 2 c operation refer to lis3lv02dq datasheet or contact st technical support. 5.1 spi bus interface the AIS326DQ spi is a bus slave. the spi allows to write and read the registers of the device. the serial interface interacts with the outside world with 4 wires: cs , spc , sdi and sdo . figure 5. read and write protocol cs is the serial port enable and it is controlled by the spi master. it goes low at the start of the transmission and goes back high at the end. spc is the serial port clock and it is controlled by the spi master. it is stopped high when cs is high (no transmission). sdi and sdo are respectively the serial port data input and output. those lines are driven at the falling edge of spc and should be captured at the rising edge of spc . both the read register and write register commands are completed in 16 clock pulses or in multiple of 8 in case of multiple byte read/w rite. bit duration is the time between two falling edges of spc . the first bit (bit 0) starts at the first falling edge of spc after the falling edge table 7. serial interface pin description pin name pin description cs chip select (logic 0: spi enabled, logic 1: spi disabled) spc spi serial port clock sdi/sdo spi serial data input (sdi) 3-wire interface serial data output (sdo) sdo spi serial data output (sdo) cs spc sdi sdo rw ad5 ad4 ad3 ad2 ad1 ad0 di7di6di5di4di3di2di1di0 do7 do6 do5 do4 do3 do2 do1 do0 ms
digital interface AIS326DQ 20/51 doc id 14956 rev 4 of cs while the last bit (bit 15, bit 23, ...) starts at the last falling edge of spc just before the rising edge of cs . bit 0 : rw bit. when 0, the data di(7:0) is written into the device. when 1, the data do(7:0) from the device is read. in latter case, the chip will drive sdo at the start of bit 8. bit 1 : ms bit. when 0, the address will remain unch anged in multiple r ead/write commands. when 1, the address will be auto increased in multip le read/write commands. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (wri te mode). this is the data that will be written into the device (msb first). bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). in multiple read/write comman ds further blocks of 8 clock periods will be added. when ms bit is 0 the address used to read/write data remains the same for every block. when ms bit is ?1? the address used to read/write data is increased at every block. the function and the behavior of sdi and sdo remain unchanged. 5.1.1 spi read figure 6. spi read protocol the spi read command is performed with 16 clock pulses. multiple byte read command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). bit 16-... : data do(...-8). further da ta in multiple byte reading. cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
AIS326DQ digital interface doc id 14956 rev 4 21/51 figure 7. multiple bytes spi read protocol (2 bytes example) 5.1.2 spi write figure 8. spi write protocol the spi write command is performed with 16 cl ock pulses. multiple by te write command is performed adding blocks of 8 clock pulses at the previous one. bit 0 : write bit. the value is 0. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple writing. bit 2 -7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data di(7:0) (wri te mode). this is th e data that will be writ ten inside the device (msb first). bit 16-... : data di(...-8). further data in multiple byte writing. figure 9. multiple bytes spi write protocol (2 bytes example) cs spc sdi sdo rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 do15 do14 do13 do12 do11 do10 do9 do8 ms cs spc sdi rw di7 di6 di5 di4 di3 di2 di1 di0 ad5 ad4 ad3 ad2 ad1 ad0 ms cs spc sdi rw ad5 ad4 ad3 ad2 ad1 ad0 di7 di6 di5 di4 di3 di2 di1 di0 di15 di14 di13 di12 di11 di10 di9 di8 ms
digital interface AIS326DQ 22/51 doc id 14956 rev 4 5.1.3 spi read in 3-wires mode 3-wires mode is entered by sett ing to ?1? bit sim (spi serial interface mode selection) in ctrl_reg2. figure 10. spi read protocol in 3-wires mode the spi read command is performed with 16 clock pulses: bit 0 : read bit. the value is 1. bit 1 : ms bit. when 0 do not increment address, when 1 increment address in multiple reading. bit 2-7 : address ad(5:0). this is the address field of the indexed register. bit 8-15 : data do(7:0) (read mode). this is the da ta that will be read from the device (msb first). multiple read command is also available in 3-wires mode. cs spc sdi/o rw do7 do6 do5 do4 do3 do2 do1 do0 ad5 ad4 ad3 ad2 ad1 ad0 ms
AIS326DQ register mapping doc id 14956 rev 4 23/51 6 register mapping the table given below provides a listing of the 8 bit registers embedded in the device and the related address. table 8. registers address map register name type register address default comment binary hex rw 0000000 - 0001110 00 - 0e reserved who_am_i r 0001111 0f 00111010 dummy register rw 0010000 - 0010101 10 - 15 reserved offset_x rw 0010110 16 calibration loaded at boot offset_y rw 0010111 17 calibration loaded at boot offset_z rw 0011000 18 calibration loaded at boot gain_x rw 0011001 19 calibration loaded at boot gain_y rw 0011010 1a calibration loaded at boot gain_z rw 0011011 1b calibration loaded at boot 0011100 -0011111 1c-1f reserved ctrl_reg1 rw 0100000 20 00000111 ctrl_reg2 rw 0100001 21 00000000 ctrl_reg3 rw 0100010 22 00001000 hp_filter reset r 0100011 23 dummy dummy register 0100100-0100110 24-26 not used status_reg rw 0100111 27 00000000 outx_l r 0101000 28 output outx_h r 0101001 29 output outy_l r 0101010 2a output outy_h r 0101011 2b output outz_l r 0101100 2c output outz_h r 0101101 2d output r 0101110 2e reserved 0101111 2f not used ff_wu_cfg rw 0110000 30 00000000 ff_wu_src rw 0110001 31 00000000 ff_wu_ack r 0110010 32 dummy dummy register 0110011 33 not used ff_wu_ths_l rw 0110100 34 00000000
register mapping AIS326DQ 24/51 doc id 14956 rev 4 registers marked as reserved must not be changed. the writing to those registers may cause permanent damages to the device. the content of the registers that are loaded at boot should not be changed. they contain the factory calibration values. their content is automatically restored when the device is powered up. ff_wu_ths_h rw 0110101 35 00000000 ff_wu_duration rw 0110110 36 00000000 0110111 37 not used dd_cfg rw 0111000 38 00000000 dd_src rw 0111001 39 00000000 dd_ack r 0111010 3a dummy dummy register 0111011 3b not used dd_thsi_l rw 0111100 3c 00000000 dd_thsi_h rw 0111101 3d 00000000 dd_thse_l rw 0111110 3e 00000000 dd_thse_h rw 0111111 3f 00000000 1000000-1111111 40-7f reserved table 8. registers address map (continued) register name type register address default comment binary hex
AIS326DQ register description doc id 14956 rev 4 25/51 7 register description the device contains a set of registers which are used to control its behavior and to retrieve acceleration data. the registers 7.2 to 7.7 contain the factory calibration values, it is not necessary to change their value for normal device operation. 7.1 who_am_i (0fh) addressing this register the physical address of the device is returned. for AIS326DQ the physical address assigned in factory is 3ah. 7.2 offset_x (16h) 7.3 offset_y (17h) table 9. register w7 w6 w5 w4 w3 w2 w1 w0 table 10. register description w7, w0 AIS326DQ physical address equal to 3ah table 11. offset_x register ox7ox6ox5ox4ox3ox2ox1ox0 table 12. offset_x register description ox7, ox0 digital offset trimming for x-axis table 13. offset_y register oy7 oy6 oy5 oy4 oy3 oy2 oy1 oy0 table 14. offset_y register description oy7, oy0 digital offset trimming for y-axis
register description AIS326DQ 26/51 doc id 14956 rev 4 7.4 offset_z (18h) 7.5 gain_x (19h) 7.6 gain_y (1ah) 7.7 gain_z (1bh) table 15. offset_z register oz7 oz6 oz5 oz4 oz3 oz2 oz1 oz0 table 16. offset_z register description oz7, oz0 digital offs et trimming for z-axis table 17. gain_x register gx7gx6gx5gx4gx3gx2gx1gx0 table 18. gain_x register description gx7, gx0 digital gain trimming for x-axis table 19. gain_y register gy7gy6gy5gy4gy3gy2gy1gy0 table 20. gain_y register description gy7, gy0 digital gain trimming for y-axis table 21. gain_z register gz7 gz6 gz5 gz4 gz3 gz2 gz1 gz0 table 22. gain_z register description gz7, gz0 digital gain trimming for z-axis
AIS326DQ register description doc id 14956 rev 4 27/51 7.8 ctrl_reg1 (20h) pd1, pd0 bit allows to turn the device out of power-down mode. the device is in power- down mode when pd1, pd0= ?00? (default value after boot). the device is in normal mode when either pd1 or pd0 is set to 1. df1, df0 bit allows to select the data rate at which acceleration samples are produced. the default value is ?00? which corresponds to a data-rate of 40 hz. by changing the content of df1, df0 to ?01?, ?10? and ?11? the selected data-rate will be set respectively equal to 160 hz, 640 hz and to 2560 hz. st bit is used to activate the self test function. when the bit is set to one, an output change will occur to the device outputs (refer to tabl e 2 and 3 for specification) thus allowing to check the functionality of the whole measurement chain. zen bit enables the z-axis measurement channel when set to 1. the default value is 1. yen bit enables the y-axis measurement channel when set to 1. the default value is 1. xen bit enables the x-axis measurement channel when set to 1. the default value is 1. 7.9 ctrl_reg2 (21h) table 23. ctrl_reg1 register pd1 pd0 df1 df0 st zen yen xen table 24. ctrl_reg1 register description pd1, pd0 power down control (00: power-down mode; 01, 10, 11: device on) df1, df0 decimation factor control (00: decimate by 512; 01: decimate by 128; 10: decimate by 32; 11: decimate by 8) st self test enable (0: normal mode; 1: self-test active) zen z-axis enable (0: axis off; 1: axis on) ye n y-axis enable (0: axis off; 1: axis on) xen x-axis enable (0: axis off; 1: axis on) table 25. ctrl_reg2 register fs bdu ble boot ien drdy sim das
register description AIS326DQ 28/51 doc id 14956 rev 4 fs bit is used to select full scale value. after the device power-up the default full scale value is +/-2 g . in order to obtain a +/-6 g full scale it is necessary to set fs bit to ?1?. bdu bit is used to inhibit output registers update between the reading of upper and lower register parts. in default mode (bdu = ?0?) the lower and upper register parts are updated continuously. if it is not sure to read faster than output data rate, it is recommended to set bdu bit to ?1?. in this way, after the reading of the lower (upper) register part, the content of that output registers is not updated until the upper (lower) part is read too. this feature avoids reading lsb and msb related to different samples. ble bit is used to select big endian or little endian representation for output registers. in big endian?s one msb acceleration value is located at addresses 28h (x-axis), 2ah (y-axis) and 2ch (z-axis) while lsb acceleration value is located at addresses 29h (x-axis), 2bh (y- axis) and 2dh (z-axis). in little endian repres entation (default, ble=?0?) the order is inverted (refer to data register description for more details). boot bit is used to refresh the content of internal registers stored in the flash memory block. at the device power up the content of the flash memory block is transferred to the internal registers related to trimming functions to permit a good behavior of the device itself. if for any reason the content of trimming registers was changed it is sufficient to use this bit to restore correct values. when boot bit is set to ?1? the content of internal flash is copied inside corresponding internal registers and it is used to calibrate the device. these values are factory trimmed and they are different for every accelerometer. they permit a good behavior of the device and normally they have not to be changed. at the end of the boot process the boot bit is set again to ?0?. ien bit is used to switch the value present on data-ready pad between data-ready signal and interrupt signal. at power up the data-ready signal is chosen. it is however necessary to modify drdy bit to enable data-ready signal generation. table 26. ctrl_reg2 register description fs full scale selection (0: 2 g ; 1: 6 g ) bdu block data update (0: continuous update; 1: output regi sters not updated between msb and lsb reading) ble big/little endian selection (0: little endian; 1: big endian) boot reboot memory content ien interrupt enable (0: data ready on rdy pad; 1: interrupt events on rdy pad) drdy enable data-ready generation sim spi serial interface mode selection (0: 4-wire interface; 1: 3-wire interface) das data alignment selection (0: 12 bit right justified; 1: 16 bit left justified)
AIS326DQ register description doc id 14956 rev 4 29/51 drdy bit is used to enable data-ready (rdy/int) pin activation. if drdy bit is ?0? (default value) on data-ready pad a ?0? value is present. if a data-ready signal is desired it is necessary to set to ?1? drdy bit. data-ready signal goes to ?1? whenever a new data is available for all the enabled axis. for example if z-axis is disabled, data-ready signal goes to ?1? when new values are available for both x and y axis. data-ready signal comes back to ?0? when all the registers containing values of the enabled axis are read. to be sure not to loose any data coming from the accelerometer data registers must be read before a new data-ready rising edge is gene rated. in this ca se data-ready signal will have the same frequency of the data rate chosen. sim bit selects the spi serial interface mode. when sim is ?0? (default value) the 4-wire interface mode is selected. the data coming from the device are sent to sdo pad. in 3-wire interface mode output data are sent to sda/sdi pad. das bit permits to decide between 12 bit right justified and 16 bit left justified representation of data coming from the device. the first case is the default case and the most significant bits are replaced by the bit representing the sign. 7.10 ctrl_reg3 (22h) fds bit enables (fds=1) or bypass (fds=0) the high pass filter in the signal chain of the sensor. table 27. ctrl_reg3 register eck hpdd hpff fds res res cfs1 cfs0 table 28. ctrl_reg3 register description eck external clock. default value: 0 (0: clock from internal oscillator; 1: clock from external pad) hpdd high pass filter enabled for direction detection. default value: 0 (0: filter bypassed; 1: filter enabled) hpff high pass filter enabled for free-fall and wake-up. default value: 0 (0: filter bypassed; 1: filter enabled) fds filtered data selection. default value: 0 (0: internal filter bypassed; 1: data from internal filter) cfs1, cfs0 high-pass filter cut-off frequency selection. default value: 00 (00: hpc=512 01: hpc=1024 10: hpc=2048 11: hpc=4096)
register description AIS326DQ 30/51 doc id 14956 rev 4 cfs1, cfs0 bits defines the coefficient hpc to be used to calculate the -3db cut-off frequency of the high pass filter: 7.11 hp_filter_reset (23h) dummy register. reading at this address zeroes instantaneously the content of the internal high pass-filter. read data is not significant. 7.12 status_reg (27h) the content of this register is updated every odr cycle, regardless of bdu bit value in ctrl_reg2. 7.13 outx_l (28h) f cutoff 0.318 hpc -------------- - odrx 2 ---------------- - ? = table 29. status_reg register zyxor zor yor xor zyxda zda yda xda table 30. status_reg register description zyxor x, y and z axis data overrun zor z axis data overrun yor y axis data overrun xor x axis data overrun zyxda x, y and z axis new data available zda z axis new data available yda y axis new data available xda x axis new data available table 31. outx_l register xd7 xd6 xd5 xd4 xd3 xd2 xd1 xd0 table 32. outx_l register description xd7, xd0 x axis acceleration data lsb
AIS326DQ register description doc id 14956 rev 4 31/51 in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the msb acceleration data and depends on bit das in ctrl_reg2 register as described in the following section. 7.14 outx_h (29h) when reading the register in ?12 bit right justified? mode the most significant bits (15:12) are replaced with bit 11 (i.e. xd15-xd12=xd11, xd11, xd11, xd11). in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the lsb acceleration data. 7.15 outy_l (2ah) in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the msb acceleration data and depends on bit das in ctrl_reg2 register as described in the following section. 7.16 outy_h (2bh) table 33. outx_h register xd15 xd14 xd13 xd12 xd11 xd10 xd9 xd8 table 34. outx_h register description xd15, xd8 x axis acceleration data msb table 35. outy_l register yd7 yd6 yd5 yd4 yd3 yd2 yd1 yd0 table 36. outy_l register description yd7, yd0 y axis acceleration data lsb table 37. outy_h register yd15 yd14 yd13 yd12 yd11 yd10 yd9 yd8 table 38. outy_h register description yd15, yd8 y axis acceleration data msb
register description AIS326DQ 32/51 doc id 14956 rev 4 when reading the register in ?12 bit right justified? mode the most significant bits (15:12) are replaced with bit 11 (i.e. yd15-yd12=yd11, yd11, yd11, yd11). in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the lsb acceleration data. 7.17 outz_l (2ch) in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the msb acceleration data and depends on bit das in ctrl_reg2 register as described in the following section. 7.18 outz_h (2dh) when reading the register in ?12 bit right justified? mode the most significant bits (15:12) are replaced with bit 11 (i.e. zd15 -zd12=zd11, zd11, zd11, zd11). in big endian mode (bit ble in ctrl_reg2 set to ?1?) the content of this register is the lsb acceleration data. table 39. outz_l register zd7 zd6 zd5 zd4 zd3 zd2 zd1 zd0 table 40. outz_l register description zd7, zd0 z axis acceleration data lsb table 41. outz_h register zd15 zd14 zd13 zd12 zd11 zd10 zd9 zd8 table 42. outz_h register description zd15, zd8 z axis acceleration data msb
AIS326DQ register description doc id 14956 rev 4 33/51 7.19 ff_wu_cfg (30h) free-fall and inertial wake-up configuration register. table 43. ff_wu_cfg register aoi lir zhie zlie yhie ylie xhie xlie table 44. ff_wu_cfg register description aoi and/or combination of interrupt events. default value: 0. (0: or combination of interrupt events; 1: and combination of interrupt events) lir latch interrupt request. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) zhie enable interrupt request on z high event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) zlie enable interrupt request on z low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt request on y high event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) ylie enable interrupt request on y low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt request on x high event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value higher than preset threshold) xlie enable interrupt request on x low event. default value: 0. (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold)
register description AIS326DQ 34/51 doc id 14956 rev 4 7.20 ff_wu_src (31h) 7.21 ff_wu_ack (32h) dummy register. if lir bit in ff_wu_cfg register is set to ?1?, a reading at this address refreshes the ff_wu_src register. read data is not significant. 7.22 ff_wu_ths_l (34h) 7.23 ff_wu_ths_h (35h) table 45. ff_wu_src register x ia zhzlyhylxhxl table 46. ff_wu_src register description ia interrupt active. default value: 0 (0: no interrupt has been generated; 1: one or more interrupt events have been generated) zh z high. default value: 0 (0: no interrupt; 1: z high event has occurred) zl z low. default value: 0 (0: no interrupt; 1: z low event has occurred) yh y high. default value: 0 (0: no interrupt; 1: y high event has occurred) yl y low. default value: 0 (0: no interrupt; 1: y low event has occurred) xh x high. default value: 0 (0: no interrupt; 1: x high event has occurred) xl x low. default value: 0 (0: no interrupt; 1: x low event has occurred) table 47. ff_wu_ths_l register ths7 ths6 ths5 ths4 ths3 ths2 ths1 ths0 table 48. ff_wu_ths_l register description ths7, ths0 free-fall / inertial wake up acceleration threshold lsb table 49. ff_wu_ths_h register ths15 ths14 ths13 ths12 ths11 ths10 ths9 ths8
AIS326DQ register description doc id 14956 rev 4 35/51 table 50. ff_wu_ths_h register description ths15, ths8 free-fall / inertial wake up acceleration threshold msb
register description AIS326DQ 36/51 doc id 14956 rev 4 7.24 ff_wu_duration (36h) this register sets the minimum duration of the free-fall/wake-up event to be recognized. 7.25 dd_cfg (38h) table 51. ff_wu_duration register fwd7 fwd6 fwd5 fwd4 fwd3 fwd2 fwd1 fwd0 table 52. ff_wu_duration register description fwd7, fwd0 minimum duration of the free-fall/wake-up event duration s () ff_wu_duration (dec) odr ----------------------------------------------------------------------- - = table 53. dd_cfg register iend lir zhie zlie yhie ylie xhie xlie table 54. dd_cfg register description iend interrupt enable on direction change. default value: 0 (0: disabled; 1: interrupt signal enabled) lir latch interrupt request into dd_src reg with the dd_src reg cleared by reading dd_ack reg. default value: 0. (0: interrupt request not latched; 1: interrupt request latched) zhie enable interrupt generation on z high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured acce l. value higher than preset threshold) zlie enable interrupt generation on z low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) yhie enable interrupt generation on y high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured acce l. value higher than preset threshold)
AIS326DQ register description doc id 14956 rev 4 37/51 direction-detector configuration register. 7.26 dd_src (39h) ylie enable interrupt generation on y low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) xhie enable interrupt generation on x high event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured acce l. value higher than preset threshold) xlie enable interrupt generation on x low event. default value: 0 (0: disable interrupt request; 1: enable interrupt request on measured accel. value lower than preset threshold) table 54. dd_cfg register description (continued) table 55. dd_src register x ia zhzlyhylxhxl table 56. dd_src register description ia interrupt event from direction change. (0: no direction changes detected; 1: direction has changed from previous measurement) zh z high. default value: 0 (0: z below thsi threshold; 1: z accel. exceeding thse threshold along positive direction of acceleration axis) zl z low. default value: 0 (0: z below thsi threshold; 1: z accel. exceeding thse threshold along negative direction of acceleration axis) yh y high. default value: 0 (0: y below thsi threshold; 1: y accel. exceeding thse threshold along positive direction of acceleration axis) yl y low. default value: 0 (0: y below thsi threshold; 1: y accel. exceeding thse threshold along negative direction of acceleration axis) xh x high. default value: 0 (0: x below thsi threshold; 1: x accel. exceeding thse threshold along positive direction of acceleration axis) xl x low. default value: 0 (0: x below thsi threshold; 1: x accel. exceeding thse threshold along negative direction of acceleration axis)
register description AIS326DQ 38/51 doc id 14956 rev 4 direction detector source register. 7.27 dd_ack (3ah) dummy register. if lir bit in dd_cfg register is set to ?1?, a reading at this address refreshes the dd_src register. read data is not significant. 7.28 dd_thsi_l (3ch) 7.29 dd_thsi_h (3dh) 7.30 dd_thse_l (3eh) 7.31 dd_thse_h (3fh) table 57. dd_thsi_l register thsi7 thsi6 thsi5 thsi4 thsi3 thsi2 thsi1 thsi0 table 58. dd_thsi_l register description thsi7, thsi0 direction detection internal threshold lsb table 59. dd_thsi_h register thsi15 thsi14 thsi13 thsi12 thsi11 thsi10 thsi9 thsi8 table 60. dd_thsi_h register description thsi15, thsi8 direction detection internal threshold msb table 61. dd_thse_l register thse7 thse6 thse5 thse4 thse3 thse2 thse1 thse0 table 62. dd_thse_l register description thse7, thse0 direction detection external threshold lsb table 63. dd_thse_h register thse15 thse14 thse13 thse12 thse11 thse10 thse9 thse8
AIS326DQ register description doc id 14956 rev 4 39/51 table 64. dd_thse_h register description thse15, thse8 direction detection external threshold msb
typical performance characteristics AIS326DQ 40/51 doc id 14956 rev 4 8 typical performance characteristics 8.1 mechanical characteristics at 25 c figure 11. x-axis zero- g level at 3.3 v figure 12. x-axis sensitivity at 3.3 v figure 13. y-axis zero- g level at 3.3 v figure 14. y-axis sensitivity at 3.3 v figure 15. z-axis zero- g level at 3.3 v figure 16. z-axis sensitivity at 3.3 v ?80 ?60 ?40 ?20 0 20 40 60 80 0 5 10 15 20 25 30 35 40 45 zero?g level offset [mg] percent of parts [%] 940 960 980 1000 1020 1040 1060 1080 1100 1120 0 5 10 15 20 25 30 sensitivity [lsb/g] percent of parts [%] ?80 ?60 ?40 ?20 0 20 40 60 80 0 5 10 15 20 25 30 35 40 zero?g level offset [mg] percent of parts [%] 940 960 980 1000 1020 1040 1060 1080 1100 1120 0 5 10 15 20 25 30 sensitivity [lsb/g] percent of parts [%] ?80 ?60 ?40 ?20 0 20 40 60 80 0 5 10 15 20 25 30 zero?g level offset [mg] percent of parts [%] 940 960 980 1000 1020 1040 1060 1080 1100 1120 0 5 10 15 20 25 30 35 sensitivity [lsb/g] percent of parts [%]
AIS326DQ typical performance characteristics doc id 14956 rev 4 41/51 8.2 mechanical characteristics at -40 c figure 17. x-axis zero-g level at 3.3 v figure 18. x-axis sensitivity at 3.3 v figure 19. y-axis zero- g level at 3.3 v figure 20. y-axis sensitivity at 3.3 v figure 21. z-axis zero- g level at 3.3 v figure 22. z-axis sensitivity at 3.3 v ?80 ?60 ?40 ?20 0 20 40 60 80 0 5 10 15 20 25 30 35 40 zero?g level offset [mg] percent of parts [%] 940 960 980 1000 1020 1040 1060 1080 1100 1120 0 5 10 15 20 25 30 sensitivity [lsb/g] percent of parts [%] ?80 ?60 ?40 ?20 0 20 40 60 80 0 5 10 15 20 25 30 35 40 45 zero?g level offset [mg] percent of parts [%] 940 960 980 1000 1020 1040 1060 1080 1100 1120 0 5 10 15 20 25 30 sensitivity [lsb/g] percent of parts [%] ?80 ?60 ?40 ?20 0 20 40 60 80 0 5 10 15 20 25 zero?g level offset [mg] percent of parts [%] 940 960 980 1000 1020 1040 1060 1080 1100 1120 0 5 10 15 20 25 30 sensitivity [lsb/g] percent of parts [%]
typical performance characteristics AIS326DQ 42/51 doc id 14956 rev 4 8.3 mechanical characteristics at 105 c figure 23. x-axis zero- g level at 3.3 v figure 24. x-axis sensitivity at 3.3 v figure 25. y-axis zero- g level at 3.3 v figure 26. y-axis sensitivity at 3.3 v figure 27. z-axis zero- g level at 3.3 v figure 28. z-axis sensitivity at 3.3 v ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 0 5 10 15 20 25 zero?g level offset [mg] percent of parts [%] 920 940 960 980 1000 1020 1040 1060 1080 1100 0 5 10 15 20 25 30 sensitivity [lsb/g] percent of parts [%] ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 0 5 10 15 20 25 30 35 zero?g level offset [mg] percent of parts [%] 940 960 980 1000 1020 1040 1060 1080 1100 1120 0 5 10 15 20 25 30 sensitivity [lsb/g] percent of parts [%] ?150 ?100 ?50 0 50 100 150 0 5 10 15 20 25 zero?g level offset [mg] percent of parts [%] 920 940 960 980 1000 1020 1040 1060 1080 1100 0 5 10 15 20 25 30 sensitivity [lsb/g] percent of parts [%]
AIS326DQ typical performance characteristics doc id 14956 rev 4 43/51 8.4 mechanical characteristics de rived from measurement in the -40 c to +105 c temperature range figure 29. x-axis zero- g level change vs. temperature at 3.3 v figure 30. x-axis sensitivity change vs. temperature at 3.3 v figure 31. y-axis zero- g level change vs. temperature at 3.3 v figure 32. y-axis sensitivity change vs. temperature at 3.3 v figure 33. z-axis zero- g level change vs. temperature at 3.3 v figure 34. z-axis sensitivity change vs. temperature at 3.3 v ?50 ?25 0 25 50 75 100 125 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 temp [ o c] zero?g level [mg] ?50 ?25 0 25 50 75 100 125 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 temp [ o c] sensitivity [%] ?50 ?25 0 25 50 75 100 125 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 temp [ o c] zero?g level [mg] ?50 ?25 0 25 50 75 100 125 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 temp [ o c] sensitivity [%] ?50 ?25 0 25 50 75 100 125 ?100 ?80 ?60 ?40 ?20 0 20 40 60 80 100 temp [ o c] zero?g level [mg] ?50 ?25 0 25 50 75 100 125 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 temp [ o c] sensitivity [%]
typical performance characteristics AIS326DQ 44/51 doc id 14956 rev 4 8.5 electro-mechanical ch aracteristics at 25 c figure 35. x and y axes zero- g level as function of supply voltage figure 36. x and y axes sensitivity as function of supply voltage figure 37. z axis zero- g level as function of supply voltage figure 38. z axis sensitivity as function of supply voltage 3 3.1 3.2 3.3 3.4 3.5 3.6 ?80 ?60 ?40 ?20 0 20 40 60 80 vdd [v] normalized zero?g level [mg] 3 3.1 3.2 3.3 3.4 3.5 3.6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 vdd [v] normalized sensitivity [%] 3 3.1 3.2 3.3 3.4 3.5 3.6 ?80 ?60 ?40 ?20 0 20 40 60 80 vdd [v] normalized zero?g level [mg] 3 3.1 3.2 3.3 3.4 3.5 3.6 ?5 ?4 ?3 ?2 ?1 0 1 2 3 4 5 vdd [v] normalized sensitivity [%]
AIS326DQ typical performance characteristics doc id 14956 rev 4 45/51 8.6 electrical characteristics at 25 c 8.7 electrical charac teristics at -40 c 8.8 electrical charac teristics at 105 c figure 39. current consumption in power- down mode (vdd=3.3 v) figure 40. current consumption in operational mode (vdd=3.3 v) figure 41. current consumption in power- down mode (vdd=3.3 v) figure 42. current consumption in operational mode (vdd=3.3 v) figure 43. current consumption in power- down mode (vdd=3.3 v) figure 44. current consumption in operational mode (vdd=3.3 v) ?2 ?1 0 1 2 3 4 5 6 7 0 5 10 15 20 25 current consumption [ua] percent of parts [%] 500 550 600 650 700 750 800 850 0 5 10 15 20 25 current consumption [ua] percent of parts [%] ?2 ?1 0 1 2 3 4 5 6 7 0 5 10 15 20 25 30 current consumption [ua] percent of parts [%] 500 550 600 650 700 750 800 850 0 5 10 15 20 25 current consumption [ua] percent of parts [%] ?2 ?1 0 1 2 3 4 5 6 7 0 5 10 15 20 25 30 current consumption [ua] percent of parts [%] 500 550 600 650 700 750 800 850 0 5 10 15 20 25 30 35 current consumption [ua] percent of parts [%]
soldering information AIS326DQ 46/51 doc id 14956 rev 4 9 soldering information the qfpn-28 package is compliant with the ecopack ? , rohs and ?green? standard. it is qualified for soldering heat resistance according to jedec j- std-020c, in msl3 condition. land pattern and soldering recommendations are also available at www.st.com/ . 9.1 general guidelines abou t soldering surface mount accelerometer as common pcb design and industrial practice when considering accelerometer soldering, there are always 3 elements to take into consideration: 1. pcb with its own conductive layers (i.e. copper) and other organic materials used for board protection and dielectric isolation. 2. accelerometer to be mounted on the board. accelerometer senses acceleration, but it senses also the mechanical stress coming from the board. this stress is minimized with simple pcb design rules. 3. soldering paste like snagcu. this soldering paste can be dispensed on the board with a screen printing method through a stencil. the pattern of the soldering paste on the pcb is given by the stencil mask itself. 9.2 pcb design guidelines pcb land and solder masking general recommendations are shown in figure 45 . refer to figure 46 for specific device size, land count and pitch. it is recommended to open solder mask external to pcb land; it is mandatory, for correct device functionality, that some clearance is ensured to be present between accelerometer thermal pad and pcb. in order to obtain this clearance it is recommended to open the pcb thermal pad solder mask; the area below the sensor (on the same side of the board) must be defined as keep- out area. it is strongly recommended not to place any structure in top metal layer underneath the sensor; traces connected to pads should be as much symmetric as possible. symmetry and balance for pad connection will help component self alignm ent and will lead to a better control of solder paste reduction after reflow; for better performances over temperature it is strongly recommended not to place large insertion components like buttons or shielding boxes at distance less than 2 mm from the sensor; central die pad and ?pin 1 indicator? are physically connected to gnd. leave ?pin 1 indicator? unconnected during soldering.
AIS326DQ soldering information doc id 14956 rev 4 47/51 9.2.1 pcb design rules figure 45. recommended land and solder mask design for qfpn packages a = clearance from pcb land edge to solder mask opening 0.1 mm to ensure that some solder mask remains between pcb pads b = pcb land length = qfpn solder pad length + 0.1 mm c = pcb land width = qfpn solder pad width + 0.1 mm d = pcb thermal pad solder mask opening = qfpn thermal pad side + 0.2 mm 9.3 stencil design and solder paste application the thickness and the pattern of the soldering paste are important for the proper accelerometer mounting process. stainless steel stencils are recommended for solder paste application a stencil thickness of 125 - 150 m (5 - 6 mils) is recommended for screen printing the final thickness of soldering paste should allow proper cleaning of flux residuals and clearance between sensor package and pcb stencil aperture should have rectangular shape with dimension up to 25 m (1mil) smaller than pcb land the openings of the stencil for the signal pads should be between 50% and 80% of the pcb pad area optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded the fine pitch of the ic leads requires accurate alignment of the stencil to the printed circuit board. the stencil and printed circuit assembly should be aligned to within 25 m (1 mil) prior to applicat ion of the solder paste. package footprint pcb land solder mask opening pcb thermal pad not to be designed on pcb pcb thermal pad solder mask opening suggested to increase device thermal pad to pcb clearance a b c d
soldering information AIS326DQ 48/51 doc id 14956 rev 4 9.4 process consideration in case of use of no self-cleaning solder paste it is mandatory proper washing of the board after soldering to eliminate any possible source of leakage between adjacent pads due to flux residues the pcb soldering profile depends on the number, size and placement of components in the application board. it is not functional to define a specific soldering profile for the accelerometer only. customer should use a time and temperature reflow profile that is derived from the pcb design and manufacturing experience.
AIS326DQ package information doc id 14956 rev 4 49/51 10 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack ? is an st trademark. figure 46. qfpn-28 mechanical data and package dimensions outline and mechanical data dim. mm inch min. typ. max. min. typ. max. a 1.70 1.80 1.90 0.067 0.071 0.075 a1 0.05 0.002 a3 0.203 0.008 b 0.30 0.35 0.40 0.012 0.014 0.016 d 6.85 7.0 7.15 0.270 0.275 0.281 d1 4.90 5.00 5.10 0.192 0.197 0.20 e 6.85 7.0 7.15 0.270 0.275 0.281 e1 4.90 5.00 5.10 0.192 0.197 0.20 e 0.80 0.0315 l 0.45 0.55 0.65 0.018 0..022 0.025 l1 0.10 0.004 ddd 0.08 0.003 qfpn-28 (7x7x1.8mm) q uad f lat p ackage n o lead 7787120 c
revision history AIS326DQ 50/51 doc id 14956 rev 4 11 revision history table 65. document revision history date revision changes 20-aug-2008 1 initial release. 04-dec-2008 2 updated v st in table 3 and iddpdn in table 4 . 30-apr-2010 3 updated section 4: application hints . 01-jun-2010 4 content reworked on cover page to improve readability, no technical changes.
AIS326DQ doc id 14956 rev 4 51/51 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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